The present invention relates to electronic devices, and, more particularly, to semiconductor circuits and methods useful for filtering digital signals with a decimation of the sampling rate.
Digital Systems with Down Converters
Communications systems such broadcast radio use frequency division multiplexing (FDM) to simulaneously transmit differing information signals from several sources in a single locale. Typically, each source modulates its carrier frequency with its information signal and keeps within its allocated frequency band. Extraction of a desired information signal from a received broadband of simultaneous broadcasts may be performed by mixing down (down conversion by the selected carrier frequency) followed by lowpass filtering and demodulation as schematically illustrated by system 100 in FIG. 1. Indeed, system 100 receives radio frequency signals (e.g., 100-200 MHz) at antenna 102, filters and mixes the signals down to intermediate frequencies (e.g., 1-10 MHz) with a wideband tuner 104, converts from analog to digital format with sampling analog-to-digital converter 106, extracts the selected frequency band (e.g., of width 5 KHz) with digital down converter 108 which performs the down conversion and filtering, and demodulates and reconstructs an analog information signal with demodulator/processor 110. For example, if wideband tuner 104 has a 10 MHz output bandwidth, then analog-to-digital converter 106 will sample at 20 MHz or more (at least the Nyquist rate), and digital down converter 108 will output a 5 KHz selected band at a sampling rate of 10 KHz. That is, digital down converter 108 decimates (decreases) the sampling rate due to the small bandwidth of its output without loss of information. And this lower sampling rate implies simpler signal processing hardware may be used.
The problems of construction of system 100 include realizing digital down converter 108 operating at a high sampling frequency while maintaining a low ripple sharp cutoff filter which has programmable down conversion frequency and programmable bandwidth. Known realizations of a down conversion function include the combination of a numerically controlled oscillator/modulator (NCOM) such as the HSP45106 manufactured by Harris Corporation together with two digital decimation filters (one for the in-phase and one for the quadrature outputs of the NCOM) such as the HSP43220 also manufactured by Harris Corporation. A single chip realization such as the GC1011 digital reciver chip is manufactured by Graychip, Inc.
Crochiere and Rabiner, Multirate Digital Signal Processing (Prentice-Hall 1983) provides general information regarding signal processing using sampling rate changes.
Decimation Filters
Decimation filters provide a reduction in sampling rate. However, a simple sampling rate reduction in a signal generates an aliasing problem because frequencies which are between the original Nyquist rate and the decimated Nyquist rate will alias to frequencies is less than the decimated Nyquist rate. As a simple example, consider the analog signal cos(2.pi.ft) of frequency f sampled at an original sampling rate of f.sub.S =1/T to yield the sample stream x(n)=cos(2.pi.fnT). If the Nyquist rate f.sub.S is to be decimated by a factor of R, then the decimated signal y(m) arises from taking every Rth sample of x(n). That is, y(m)=x(Rm)=cos(2.pi.fmRT). Now if f lies between f.sub.S k/2R and f.sub.S (k+1)/2R for some integer k less than R, then cos(2.pi.[f-f.sub.S k/2R]mRT)=cos(2.pi.[f-k/2RT]mRT)=cos(2.pi.fmRT-2.pi.km)=cos(2.pi.fmRT). This shows that frequency f appears the same as frequency f-f.sub.S k/2R when the sampling rate drops from f.sub.S to f.sub.S /R. In fact, R-1 different frequencies alias to each frequency in the range 0 to f.sub.S /2R.
Consequently, a lowpass decimation filter must limit this aliasing arising from the sampling rate decimation which would otherwise appear in its passband. Aliasing outside of the passband is not a problem if a subsequent filter provides a stopband to cover this portion of the spectrum. FIG. 2 illustrates the required frequency response of a lowpass decimation filter in terms of the original sampling frequency. The broad transition band which experiences aliasing can be covered by the subsequent filter.
One approach to decimation filters appears in Hogenauer, An Economical Class of Digital Filters for Decimation and Interpolation, 29 IEEE Tr. ASSP 155 (1981). Hogenauer uses a series of integrators followed by a sample rate compressor which feeds a series of combs as illustrated schematically in FIG. 3. FIG. 3 employs standard notation: the z variable indicates a z-transform, and thus z.sup.-1 indicates a delay of one. Indeed, with a decimation rate of R and N integrators and N combs, the overall system function can be read off FIG. 3 to be H(z)=(1-z.sup.-R).sup.N /(1-z.sup.-1).sup.N which equals (1+z.sup.-1 +z.sup.-2 + . . . +z.sup.-(R+1)).sup.N. The frequency response of the filter follows from z=e.sup.j2.pi.f, so the magnitude of the frequency response equals EQU .vertline.sin(.pi.Rf)/sin(.pi.f).vertline..sup.N
FIG. 4 shows the freqeuency response magnitude with respect to the original sampling frequency. Note the nulls when Rf equals a nonzero integer; these are the centers of the bands which alias to 0.
An N-stage (N integrators and N combs) Hogenauer decimation filter can be realized as N registers and adders for the integrators and N registers and subtractors for the combs. However, at first glance such registers appear impractically large. In particular, the sum in the Nth integrator's register could increase on the order of the N power of the number of data samples which have entered the filter. But the combs take differences, and this effectively makes the absolute size of the sums in the integrator's registers insignificant. Only bits up to a most significant bit need be kept.
In more detail, the system function H(z)=(1+z.sup.-1 +z.sup.-2 + . . . +z.sup.-(R+1)).sup.N is just the z-transform of the impluse response h(m) defined by H(z)=.SIGMA.h(m)z.sup.-m. Multiplying out the Nth power polynomial easily yields h(m) which appears in FIG. 5. All of the coefficients h(m) are nonnegative because the Nth power polynomial has all nonnegative coefficients. Of course, an Nth power of a z-transform equates to an N term convolution in the time domain, so h(m) has the expected normal distribution look as follows from the Central Limit Theorem. Now the maximum filtered output data sample magnitude is just .SIGMA.h(m) times the maximum input data sample magnitude because the sequence h(m) is the impulse response. This sum may be trivially evaluated by putting z=1 in H(z)=.SIGMA.h(m)z.sup.-m and in H(z)=(1+z.sup.-1 +z.sup.-2 + . . . +z.sup.-(R-1)).sup.N to yield .SIGMA.h(m)=R.sup.N. This means that the magnitudes of the filtered output data samples are bounded by R.sup.N times the maximum magnitude of the input data samples. For example, if the input data samples were 17 bits, and the decimation rate were 1024 in a five stage filter, then the output data samples would have at most 67 bits. That is, 1024.sup.5 equals 2.sup.50, so the outputs would have at most 50 more bits than the inputs.
This increase in magnitude by a factor of R.sup.N is intuitively obvious: Let M be the maximum magnitude of the input data samples. Then during the R clocks between successive inputs to the first comb, the first integrator increases its sum by at most RM. If the input data samples had all been 0, then the first integrator's sum would be constant during these R clocks. For an initial condition of all zeros in the integrators, the following analysis is valid, and a reset prior to use will insure this. Thus during the R clocks the second integrator increases its sum by at most R(R-1)M/2 over the increase which would have occurred from all 0 data samples and the first integrator's sum constant. Similarly, the third integrator has a sum increase of at most R(R-1)(R-2)M/6 over the increase due to all 0 data samples. Hence, the Nth integrator has an increase of at most R(R-1) . . . (R-N+1)M/N! over the increase due to all 0 data samples. The increase of R(R-1) . . . (R-N+1)M/N! essentially equals R.sup.N M/N! for R much larger than N. The combs are differencers and will generate an N! factor, so maximum magnitude inputs (all with the same sign) have a net magnitude increase of about R.sup.N.
In Hogenauer's notation, if the input has bits labelled 0, 1, . . . B.sub.in -1, then the most significant bit number B.sub.MAX in the output equals the smallest integer not less than log.sub.2 R.sup.N +B.sub.in -1. That is, the gain of R.sup.N increases the number of bits by log.sub.2 R.sup.N.
The fact that the filtered output data samples have a most significant bit bounded by B.sub.MAX implies that bits greater than B.sub.MAX may be discarded in all of the registers making up the integrators and combs. This follows from modulo arithmetic because the integrators and combs just do addition and subtraction. More heuristically, the last comb takes the difference of two numbers, say A and B, which coincide for all bits above B.sub.MAX, so discarding such coincident bits will not affect the difference output. In the next to last comb, the output A is the difference of two numbers, say L and M, and the output B is the difference of two numbers, M and say N. But the bits greater than B.sub.MAX in L differ from those in M by the same amount that those in M differ from those in N, so if all of these bits were discarded, there would be no loss of information. Similarly, going back to the first comb; note that this is just the reverse of the observation of increases in the integrators due to 0 data samples and the further increases or decreases from informational data samples. Because the first comb may discard bits greater than B.sub.MAX, these bits may be discarded in the last integrator. Similarly, going back through the integrators because they add, all bits greater than B.sub.MAX may be discarded.
Hogenauer also shows that the least significant bits in the integrator and comb registers can be truncated (and thereby shrink the register sizes) at levels which generate less error than the quantization noise of the output. In particular, let h.sub.j (m) be the impulse response for input directly into the jth integrator. Thus truncation of B bits in the jth integrator produces a noise with mean 2.sup.B /2 and variance 2.sup.2B /12 in this jth integrator which leads to a noise with variance (2.sup.2B /12)(.SIGMA.h.sub.j (m).sup.2) at the output because the impulse response coefficients multiply uncorrelated independent inputs. Hence, truncation or rounding of B.sub.2N+1 bits at the output will generate output noise with variance at least as great as the variance of the output noise generated by the truncation of B bits in the jth integrator provided that, roughly, B is no greater than B.sub.j with: EQU B.sub.j =B.sub.2N+1 -[log.sub.2 (.SIGMA.h.sub.j (m).sup.2)]/2
Computation of the h.sub.j (m) is straightforward. A similar condition holds for the combs which Hogenauer labels with j running from N+1 to 2N, and thus the notation B.sub.2N+1 for the output bit numbers. This B.sub.j definition differs slightly from that in Hogenauer who takes the sum of the variances of the truncation noises generated in all N integrators and N combs as not exceeding the noise generated by output truncation or rounding. FIG. 6 heuristically illustrates the integrator and comb registers without the adders and subtractors for the case of 5 stages; bits transfer horizontally. FIG. 6 also shows B.sub.MAX and bit truncations B.sub.j for the case of decimation rate R equal to 2.sup.15, 17-bit input (B.sub.in =17) so B.sub.MAX =91, and 18-bit output (B.sub.2N+1 =73). In particular, note that rather than a total of 920 register bits, only 403 total register bits are needed.
FIG. 7 heuristically shows the registers of a decimating filter made of integrators and combs and with an input multiplexer which provides a programmable decimation rate as follows. Presume a maximum decimation rate of 2.sup.13, a filter with five stages, input data samples with 17 bits, and output samples with 18 bits. Thus B.sub.MAX equals 13.times.5+17-1, or 81, so the integrator and comb registers before truncation have 82 bits numbered 0 to 81. With an 18 bit output, computing the allowable truncation B.sub.j in each register as in Hogenauer yields the register sizes shown in FIG. 7. Now if the decimation rate had instead been 2.sup.5, for example, then B.sub.MAX would have been 5.times.5+17-1, or 41. Thus the registers could have been 40 bits smaller before truncation than with the 2.sup.13 decimation rate. But the same hardware can be used as in the 2.sup.13 decimation rate filter by simply shifting the input up 40 bits as illustrated in FIG. 7 by the shifter. Indeed, any decimation rate less than 2.sup.13 can be accomodated by an appropriate shift of the input so that B.sub.MAX aligns with the MSB in the registers.
Taking the output with its MSB at B.sub.MAX in the last comb compensates for the filter gain of R.sup.5 when R is a power of 2, and makes the overall gain fall inside the range of 1/2 to 1 when R is not a power of 2. A simple example: a decimation rate of 32 implies a gain of 32.sup.5 (=2.sup.25) which means exactly 25 additional bits are required, whereas a decimation rate of 30 implies a gain of only 30.sup.5 which requires 24.534 . . . additional bits. However, bits are indivisible so 25 additional bits must be provided at the output in both cases. This means dividing out a gain of 2.sup.25 in both cases. Indeed, the gain 30.sup.5 has (unsigned) leading bits 10111001 . . . . This means the maximum magnitude of a positive output sample is 10111001 . . . rather than 11111 . . . , and the overall gain (after dividing out the 2.sup.25 gain) is 0.724 which equals 0.10111001 . . . , as expected.
However, Hogenauer's decimating filter has the problems of register size in both the integrators and combs. Every register bit also requires a further bit of adder or subtractor, and the number of bits increases rapidly as the number of filter stages increases.
Features
The present invention provides a digital decimating filter using integrators and combs with a programmable decimation rate but with the comb registers replaced by a single subtractor plus memory, and with one or more shortened integrator registers. For the shortened integrator registers, an alignment shifter permits wide decimation rate applications.